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256-position i 2 c ? -compatible digital potentiometer ad5245 rev. b in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th ir d par t ies th a t m a y r e su l t f r o m i t s use . s p e c i f ica t io n s su bj e c t t o c h an g e w i th o u t n o ti c e . n o l i c e n s e i s g r an t e d b y imp l ic a t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g d e v i c e s . t r adem ar ks and r e g i st e r ed tr ad ema r ks ar e the p r o p er t y of the i r r e sp e c t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2006 a n alog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 256-position end-t o - e nd r e s istanc e 5 k? , 1 0 k?, 50 k?, 10 0 k? c o mpac t so t - 23-8 (2. 9 mm 3 mm) package f a st settl ing ti me: t s = 5 s typ on po w e r-up f u ll r e a d /writ e of wiper r e gist er p o w e r- on pr eset t o midsc a le ex tr a pack age addr ess dec o d e pin ad 0 c o mput er sof t war e r e plac es c in fac t or y progr a mming ap plic a t ions single sup p ly : 2.7 v t o 5. 5 v l o w t e mper a t ur e c o efficient 4 5 p p m/c lo w p o we r: i dd = 8 a w i de oper a t in g t e mper a t ur e: C40c to +1 2 5 c e v al ua tion boar d a v ailable applic a t io ns mechanic al pot e ntiomet e r r e p l ac ement in n e w designs lc d p a n e l v co m adjustmen t l c d panel brig h t ness and c o ntr a st c o n t r o l t r ansducer a d justmen t of pr e ssur e , t e mper atur e , position, chemic al , and optic a l sensors rf amplifier bi asing a u t o motiv e ele c tr onics adjustmen t g a in c o ntr o l an d off s et a d just ment func ti on a l bl ock di a g r a m i 2 c i n t e r f ace w i per re g i s t e r sc l sd a ad 0 gn d v dd a w b po r 034 36 - 0 01 figure 1. pin c o nfig ur a t ion a b ad0 sd a 1 2 3 4 5 8 7 6 w v dd gn d sc l a d 5245 t o p vi ew (n o t to sc al e ) 03 43 6- 00 2 figure 2. gener a l description the ad5245 p r o v ides a com p ac t 2.9 mm 3 mm p a c k a g e d s o l u tio n f o r 256-p o si tio n ad j u s t m e n t a p p l ic a t ion s . th es e d e v i ce s pe rf o r m th e sa m e e l ectr o n i c a d j u s t m e n t fun c ti o n a s m e c h anic al p o ten t iom e t e rs o r va r i ab le r e sis t o r s, wi th enhan c e d r e s o l u t i o n , s o li d-s t a t e r e l i a b i l i t y , a nd s u p e r i o r lo w t e m p era t ur e co ef f i cien t p e r f o r ma n c e . the wi p e r s e t t i n gs a r e co n t r o l l a b l e t h r o ug h a n i 2 c-co m p a t ib le dig i tal in t e r f ace , which can als o be us e d t o r e ad bac k t h e wi p e r r e g i s t er co n t en t. ad0 can be us ed t o p l ac e u p to tw o de vices o n t h e s a m e b u s. c o mma nd b i ts a r e a v a i lab l e t o r e s e t t h e w i p e r p o si tio n t o mids cale o r t o sh u t do wn t h e de vic e in t o a s t a t e o f zer o p o w e r co nsum p t io n. o p era t in g f r o m a 2.7 v t o 5.5 v p o w e r s u p p l y and co n s u m in g l e ss t h an 8 a a l l o w s u s age i n p o r t abl e b a t t e r y - op e r a t e d ap p l i c at i o n s . n o te t h a t t h e te r m s di g i t a l p o te n t i o me t e r , v r , and r d a c are used in t e r c h a n g ea b l y .
ad5245 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 pin configuration ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 electrical characteristics ................................................................. 3 5 k? version .................................................................................. 3 10 k, 50 k?, 100 k? versions .................................................. 4 timing characteristics ..................................................................... 5 5 k?, 10 k?, 50 k?, 100 k? versions ........................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circ u its ..................................................................................... 12 theory of operation ...................................................................... 13 programming the variable resistor ......................................... 13 programming the potentiometer divider ............................... 14 esd protection ........................................................................... 14 terminal voltage operating range ......................................... 14 power-up sequence ................................................................... 14 layout and power supply bypassing ....................................... 14 constant bias to retain resistance setting ............................. 15 evaluation board ........................................................................ 15 i c interface 2 .................................................................................... 16 i c-compatible 2-wire serial bus 2 ........................................... 16 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 1/06rev. a to rev. b changes to table 3........................................................................... 5 changes to ordering guide ......................................................... 19 3/04rev. 0 to rev. a updated format................................................................ universal changes to features......................................................................... 1 changes to applications ................................................................. 1 changes to figure 1......................................................................... 1 changes to electrical characteristics5 k? version ................ 3 changes to electrical characteristics10 k?, 50 k?, and 100 k? versions ....................................................................... 4 changes to timing characteristics ............................................... 5 changes to absolute maximum ratings ...................................... 6 moved esd caution to page .......................................................... 6 changes to pin configuration and function descriptions ....... 7 changes to figures 22 and 23 ...................................................... 11 moved figure 25 to figure 26 ...................................................... 11 moved figure 26 to figure 27 ...................................................... 11 moved figure 27 to figure 25 ...................................................... 11 deleted figures 31 and 32 ............................................................ 12 changes to figure 32, figure 33 and figure 34 ......................... 12 changes to rheostat operation section..................................... 13 added figure 35............................................................................. 13 changes to equation 1 and equation 2 ...................................... 13 changes to table 6 and table 7.................................................... 13 added figure 37 ............................................................................ 14 changes to equation 4 .................................................................. 14 deleted readback rdac value section .................................... 14 deleted level shifting for bidirectional interface section ...... 14 moved esd protection section to page ..................................... 14 changes to figure 38 and figure 39............................................ 14 moved terminal voltage operating range section to page.... 14 changes to figure 40..................................................................... 14 moved power-up sequence section to page ............................. 14 moved layout and power supply bypassing section to page . 15 added constant bias to retain resistance setting section..... 15 added figure 42 ............................................................................ 15 added evaluation board section ................................................ 15 added figure 43 ............................................................................ 15 moved i 2 c interface section to page........................................... 16 changes to i2c compatible 2-wire serial bus section ........... 16 moved table 5 and table 6 to page ............................................. 17 (renumbered as table 8 and table 9) moved figure 36, figure 37, and figure 38 to page.................. 17 (renumbered as figure 44, figure 45, and figure 46) moved multiply devices on one bus section to page ............. 18 updated ordering guide ............................................................. 19 updated outline dimensions...................................................... 19 moved i 2 c disclaimer to page ..................................................... 20 5/03revision 0: initial version
ad5245 rev. b | page 3 of 20 electrical characteristics 5 k? version v dd = 5 v 10% or 3 v 10%, v a = v dd , v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C4 0.75 +4 lsb nominal resistor tolerance 3 ?r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w 50 120 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C1.5 0.6 +1.5 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C6 C2.5 0 lsb zero-scale error v wzse code = 0x00 0 2 6 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance a, b 6 c a , c b f = 1 mhz, measured to gnd, code = 0x80 90 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x80 95 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 44 w power supply sensitivity pss v dd = +5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6, 9 bandwidth C3 db bw_5k r ab = 5 k?, code = 0x80 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 2.5 k?, r s = 0 6 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, and w have no limit ations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5245 rev. b | page 4 of 20 10 k?, 50 k?, 100 k? versions v dd = 5 v 10% or 3 v 10%, v a = v dd , v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w v dd = 5 v 50 120 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C3 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 3 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance a, b 6 c a , c b f = 1 mhz, measured to gnd, code = 0x80 90 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x80 95 pf shutdown supply current i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 44 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6, 8 bandwidth C3 db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 600/100/40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage ou tput d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 all dynamic characteristics use v dd = 5 v.
ad5245 rev. b | page 5 of 20 timing characteristics 5 k?, 10 k?, 50 k?, 100 k? versions v dd = 5 v 10% or 3 v 10%, v a = v dd , v b = 0 v, C40c < t a < +125c, unless otherwise noted. table 3. parameter symbol conditions min typ 1 max unit i 2 c interface timing characteristics 2 , , 3 4 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see timing diagram ( ) for loca tions of measured values. fi gure 44 4 standard i 2 c mode operation guaranteed by design.
ad5245 r e v. b | pa ge 6 o f 2 0 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 4. p a r a me t e r v a l u e v dd to gnd C0.3 v to +7 v v a , v b , v w to gnd v dd t e rminal c u rr ent, a t o b , a t o w , b t o w 1 p u lsed 2 0 m a c o n t i n u o u s 5 m a dig i tal i n puts and o utput v o ltage t o gnd 0 v t o 7 v o p era t ing t e mper a tur e r a nge C40c to +125c m a ximum junc tion t e mpera tur e ( t jm a x ) 1 5 0 c stor age t e mpera tur e r a nge C65c to +150c l e ad t e mper a tur e (s older i ng , 10 sec) 245c ther mal r e sistanc e 2 ja : so t - 23- 8 230c/w 1 maximum terminal curr ent is boun d by the maximum current handling of the s w itches , maxi m um power d i ss ip ation of the package, and maximum appl ied vol t age acros s any two of the a , b, and w terminal s at a given resi st a n ce. 2 pa cka g e p o wer di ssi pa t i on = (t jm ax C t a )/ ja . s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (elec t r o sta t ic dischar g e) se nsitiv e device . elec tr osta tic charges as high as 4 000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wit h out det e c t ion. although this pr oduc t f e a tur es pr o p r i etar y esd pr otec ti on ci r c uitr y , per m anen t dama ge may oc cur on dev i c e s subjec ted to high energy elec tr o s ta tic di scharge s . theref or e , p r oper esd pr ec autions a r e r e com m ended to av oid per f or man c e degrada t ion or l o ss of func tiona l it y .
ad5245 r e v. b | pa ge 7 o f 2 0 pin conf igura t ion and fu nction descriptions a b ad0 sd a 1 2 3 4 5 8 7 6 w v dd gn d sc l ad5 2 4 5 t o p vi ew (n o t to sc al e ) 03 43 6- 00 2 figure 3. pin c o nfiguration ta ble 5. pi n f u nct i on d e s c ri pt i o ns p i n o . m n eonic description 1 w w t e r minal . gnd v w v dd . 2 v dd p o sitiv e p o w e r sup p ly . 3 g n d dig i tal gr ound . 4 scl serial clock i n put. p o sitiv e edge tr igger e d . p u ll-up r e sistor r e q u ir ed . 5 sd a serial da ta i n put/ o utput. p u ll-up r e sist or r e q u ir ed . 6 ad0 p r og r a mmable a ddr ess bit 0 f o r t w o - d evic e d e c o ding . 7 b b t e r minal . gnd v b v dd . 8 a a t e rminal . gnd v a v dd .
ad5245 r e v. b | pa ge 8 o f 2 0 typical perf orm ance cha r acte ristics co de ( d eci mal ) ?1 . 0 ?0 . 8 ?0 . 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 1. 0 32 09 6 64 1 2 8 1 6 0 192 224 256 rh e o s t a t m o d e i n l ( l s b ) 0. 8 5v 3v 03 436 - 0 0 3 f i gur e 4 . r - inl vs . co de vs . sup p l y v o l t a g e s 5v 3v ?1 . 0 ?0 . 8 ?0 . 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 1. 0 rhe o s t a t m o d e dnl ( l s b ) 0. 8 co de ( d eci mal ) 32 09 6 64 12 8 160 192 22 4 256 03 43 6- 00 4 f i gur e 5 . r - dnl vs . c o de vs . sup p l y v o lta g e s ?40 c + 25 c + 85 c +1 25 c ?1. 0 ?0. 8 ?0. 6 ?0 . 4 ?0 . 2 0 0. 2 0. 4 0. 6 1. 0 p o t e nt i o m e t e r m o de i n l ( l s b ) 0. 8 co de ( d eci m a l ) 32 09 6 64 128 16 0 192 2 2 4 2 56 03 43 6- 00 5 f i gur e 6 . inl vs . code vs . t e m p e r a t ur e , v dd = 5 v co de ( d ec i m a l ) ?1 . 0 ?0 . 8 ?0 . 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 1. 0 32 09 6 6 4 12 8 1 60 19 2 224 256 p o t e nt i o m e t e r m o de d n l ( l s b ) 0. 8 ?40 c + 25 c +8 5 c + 125 c 03 436 - 0 0 6 f i gur e 7 . dnl vs . c o de vs . t e m p e r a t ur e , v dd = 5 v ?1 . 0 ?0 . 8 ?0 . 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 1. 0 p o t e nt i o m e t e r m o de i n l ( l s b ) 0. 8 co de ( d eci mal ) 32 09 6 64 12 8 160 192 22 4 256 5v 3v 03 43 6- 00 7 f i gure 8. inl vs. code vs. sup p ly v o lt ages 5v 3v co de ( d eci mal ) ?1. 0 ?0. 8 ?0. 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 0. 8 32 09 6 64 1 2 8 1 6 0 192 224 256 p o t e nt i o m e t e r m o d e dn l ( l s b ) 1. 0 03 43 6- 00 8 f i gur e 9 . dnl vs . c o de vs . sup p l y v o l t a g e s
ad5245 r e v. b | pa ge 9 o f 2 0 ?1 . 0 ?0 . 8 ?0 . 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 1. 0 rhe o s t a t m o d e in l ( l s b ) 0. 8 co de ( d eci mal ) 32 09 6 64 12 8 160 192 22 4 256 c +2 5 c +8 5 c + 125 c ?40 03 43 6- 00 9 f i gur e 1 0 . r - inl vs . c o de vs . t e m p e r a t ur e , v dd = 5 v ?1 . 0 ?0 . 8 ?0 . 6 ?0. 4 ?0. 2 0 0. 2 0. 4 0. 6 1. 0 rhe o s t a t m o d e d n l ( l s b ) 0. 8 co d e ( d eci m a l ) 32 09 6 64 12 8 160 192 22 4 2 5 6 ?4 0 c +2 5 c +8 5 c + 125 c 03 43 6 - 01 0 f i gur e 1 1 . r - dnl vs . c o de vs . t e m p e r a t ur e , v dd = 5 v t e m per a t u r e ( c ) 04 0 8 0 1 2 0 ?40 0 1. 5 f s e , f u l l - s ca l e e rro r ( l s b ) 04 0 8 0 1 2 0 ?40 1. 0 2. 5 v dd = 5. 5v v dd = 2. 7v 2. 0 0. 5 0 343 6- 0 1 1 f i gure 12. f u ll- s c al e e rror v s . t e m p er a t ur e 0 4 0 8 0 120 ?4 0 0 1. 5 z s e , z e ro - s cal e e rro r ( a) t e m p e r a t ure ( c) 0 4 0 8 0 120 ?4 0 1. 0 2. 5 v dd = 5. 5v v dd = 2. 7v 2. 0 0. 5 0 3 43 6- 01 2 f i gure 13. zero -s c a le e r r o r v s . t e mpe r a t ur e te m p e r a t u r e ( c ) 0 4 0 8 0 120 ?40 0. 1 1 10 i dd s u p p l y curre nt ( a ) v dd = 5. 5 v v dd = 2. 7v 03 43 6- 01 3 f i gure 14. sup p l y current v s . t e mper at ur e i a s hut do w n cu rre nt ( n a) te m p e r a t u r e ( c ) 0 0 70 20 10 30 40 50 60 40 8 0 120 ?4 0 v dd = 5 v 03 43 6- 01 4 f i gure 15. sh u t do w n cur r ent v s . t e mper atu r e
ad5245 rev. b | page 10 of 20 co de ( d ec i m a l ) ?50 0 50 10 0 15 0 20 0 32 09 6 64 1 2 8 160 19 2 2 2 4 25 6 rh e o s t a t mo d e t e mp c o (p p m / c ) 0 34 36 - 0 1 5 f i g u re 16. r h e o s t at m o de t e mpco ?r wb /?t v s . code c o de ( d ec i m al ) ?2 0 0 20 40 60 80 100 120 140 160 32 09 6 64 12 8 160 1 9 2 224 256 p o t e nt i o m e t e r m o d e t e m p co ( p p m / c) 03 436 - 0 1 6 f i gure 1 7 . p o tentiom e ter m o de t e m p co ? v wb /? t vs . c o de 1k 10k 1 00k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x 80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 re f l e v e l 0. 000d b / di v 6. 00 0d b m arke r 1 000 0 00. 000 h z m a g ( a / r ) ?8. 91 8d b s t ar t 1 0 00. 000 h z s t o p 1 000 0 00. 000 h z 03 43 6- 01 7 f i gure 18. g a in vs. f r equ e nc y vs. c o d e , r ab = 5 k? 1k 10 k 100k 1m 0 ?6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 ?4 2 ?4 8 ?5 4 ?6 0 0x80 0x 40 0x2 0 0x1 0 0x 08 0x0 4 0x0 2 0x0 1 re f l e v e l 0. 000d b / di v 6. 00 0d b m arke r 510 634 . 725hz m a g ( a / r ) ? 9. 0 49d b s t ar t 1 0 00. 000 h z s t o p 1 000 0 00. 000 h z 03 43 6- 01 8 f i gure 19. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 k? 1k 10k 100k 1m 0 ?6 ?1 2 ?1 8 ?2 4 ?3 0 ?3 6 ?4 2 ?4 8 ?5 4 ?6 0 0x 80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 re f l e v e l 0. 000d b / di v 6. 00 0d b m arke r 100 885 . 289hz m a g ( a / r ) ? 9. 0 14d b s t ar t 1 0 00. 000 h z s t o p 1 000 0 00. 000 h z 034 36 - 0 1 9 f i gure 20. g a in vs. f r equ e nc y vs. c o d e , r ab = 50 k? 1k 10 k 100 k 1 m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x 80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 re f l e v e l 0. 000d b / di v 6. 00 0d b m arke r 54 089. 173hz m a g ( a / r ) ?9. 05 2d b s t ar t 1 0 00. 000 h z s t o p 1 000 0 00. 000 h z 03 43 6- 0 2 0 f i gure 21. g a in vs. f r equ e nc y vs. c o d e , r ab = 10 0 k?
ad5245 rev. b | page 11 of 20 10k 100 k 1 m 10m ?5. 5 ?6 . 0 ?6 . 5 ?7 . 0 ?7 . 5 ?8 . 0 ?8 . 5 ?9 . 0 ?9 . 5 ?10. 0 ?10. 5 r e f l eve l ?5. 00 0d b / di v 0. 5 00d b s t art 1 000. 0 00hz s t o p 1 000 000. 000 h z r = 5 k ? r = 10k ? r = 50 k ? r = 1 00k ? 5k ? ? 1 . 026m hz 10k ? ? 5 1 1khz 50k ? ? 101k h z 100 k ? ? 54khz 0 3 43 6- 0 2 1 f i gure 22. C3 db bandwidth @ code = 0x80 f r e q ue nc y ( h z ) 10k 100 100k 1m 1k 0 20 40 60 p s rr ( ? d b ) co d e = 0x8 0, v a = v dd , v b = 0v ps r r @ v dd = 3v dc 10% p - p a c 03 43 6- 02 2 psr r @ v dd = 5v dc 1 0% p - p a c fi g u r e 2 3 . p s r r v s . fr e q u e n c y i dd ( a) f r e q ue nc y ( h z ) 10k 800 700 600 500 400 300 900 200 100 10 0k 1m 10m 0 co de = 0 x55 co de = 0 x f f v dd = 5 v 03 43 6- 0 2 3 f i g u re 24. i dd vs . f r e q ue nc y vw scl ch 1 200m v b w c h 2 5. 00 v b w m 100n s a ch2 3 . 00 v 1 2 03 43 6- 0 2 4 f i g u re 25. lar g e s i g n al s e t t l ing ti m e , code 0x ff 0x 00 vw sc l ch 1 100m v b w ch 2 5. 00 v b w m 20 0n s a ch1 1 52mv 1 2 v a = 5 v v b = 0 v 03 43 6- 0 2 5 f i gure 2 6 . di g i ta l f eedthro u g h vw sc l ch 1 5. 00v b w ch 2 5 . 00 v b w m 2 00n s a ch 1 3. 00 v 1 2 v a = 5 v v b = 0 v 0 343 6- 026 f i g u re 27. m i ds c a l e gli t ch, cod e 0x 80 0x 7f
ad5245 rev. b | page 12 of 20 test circuits f i gur e 28 t o f i gu r e 3 4 il l u s t ra t e th e t e s t cir c ui ts tha t def i n e th e t e s t c o n d i t io n s us ed i n th e p r o d uct s p ecif ica t io n ta b l es (t abl e 1 through table 3). v ms a w b du t v+ v + = v dd 1 l sb = v+/ 2 n 03 436 - 027 f i gure 28. t e s t c i rc uit for p o tenti o meter d i v i de r n o nl in ea rit y e r r o r (inl, dnl) no co nne ct i w v ms a w b dut 03 43 6- 02 8 f i gure 29. t e s t c i rc uit for r e s i s t or p o s i tion non l i n e a r i t y e rror (r heo s ta t o p er a t ion; r - inl, r - dnl) v ms 2 v ms 1 v w a w b du t i w = v dd /r no m i n a l r w = [ v ms 1 ? v ms 2 ]/ i w 03 43 6- 0 2 9 f i gur e 3 0 . t e st c i r c ui t fo r wi p e r resi st a n c e ? v ms % dd % pss (% / % ) = v+ = v dd 10% p s r r ( d b) = 20 lo g ms dd ( ) v dd v a v ms a w b v+ ? v ? v ? v 03 436 - 0 3 0 f i gure 31. t e st c i rc uit for p o w e r sup p l y s e nsit ivit y ( p ss, pssr) + 15v ?1 5v w a 2. 5v b v ou t off s e t gn d du t ad86 1 0 v in 0 3 4 36- 03 1 f i gure 32. t e s t c i rc uit for g a in v s . f r eq uenc y w b gn d t o v dd du t i sw c o d e = 0x00 r sw = 0. 1 v i sw 0. 1 v 0 343 6- 03 2 f i gu r e 3 3 . t e st ci r c u i t fo r i n cr em en ta l on re si sta n c e w b v cm i cm a nc gn d nc v dd du t nc = no co nn e c t 0 343 6- 03 3 f i g u re 34. t e s t c i rc uit f o r co m m o n -m ode l e ak ag e cur r e n t
ad5245 rev. b | page 13 of 20 theor y of opera tion the ad5245 is a 256-p o si tion dig i tal l y co n t r o l l ed va r i a b le re s i stor ( v r ) d e v i c e . an in t e r n al p o w e r - o n p r es e t places t h e w i p e r a t mids c a le d u r i n g p o w e r - on, w h ich si m p lif i es t h e fa u l t condi t i on r e co v e r y at p o w e r- u p . programming the variable resi stor r h eos t at ope r ation the n o minal r e sis t a n c e o f t h e rd a c b e tw e e n t e r m inals a and b is a v a i la b l e in 5 k?, 10 k?, 50 k?, a nd 100 k?. the n o minal re s i st anc e ( r ab ) o f th e vr has 2 56 co n t ac t p o in ts acces s ed b y th e wi pe r t e r m in al , p l us th e b t e rm i n al co n t a c t. t h e 8-b i t da t a in t h e rd a c l a tc h is deco ded t o s e lec t on e o f t h e 256 p o s s i b l e se t t i n g s . a w b a w b a w b 034 36- 03 4 fig u re 3 5 . r h e o s t at m o de conf ig ur at i o n a s sumin g tha t a 10 k? p a r t is us ed , t h e wi p e r s f i rs t co nnec t ion s t a r ts a t t h e b t e r m inal f o r da ta 0x00. b e ca us e t h er e is a 50 ? wi p e r co n t ac t r e sist a n c e , such a co nn e c t i o n y i el ds a mi ni m u m o f 100 ? (2 5 0 ?) r e sis t a n ce betw een t e r m inals w an d b . th e s e c o n d c o n n e c ti o n i s th e fi r s t ta p po i n t , w h i c h co rr e s po n d s t o 139 ? (r wb = r ab /2 56 + 2 r w = 39 ? + 2 50 ?) f o r da t a 0 x 0 1 . the thir d co nn e c tio n is t h e n e xt ta p p o in t, r e p r es en t i n g 178 ? (2 39 ? + 2 50 ?) f o r da ta 0x02, a n d s o o n . e a c h ls b da ta v a l u e in cr ease m o v e s th e w i per u p th e r e si s t o r la dd e r un til th e las t t a p p o in t is r e ac h e d a t 10,10 0 ? (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rda c la t c h and de co de r r s r s r s r s a w b 03 43 6- 0 3 5 fi gur e 36 . ad5 245 equi va l e nt rdac ci r c ui t the g e n e ral e q u a t i o n det e r m inin g t h e dig i t a l l y p r og ra mm e d o u t p ut r e sist a n c e b e tw e e n w and b is w ab wb r r d d r 2 256 ) ( ( 1 ) w h er e: d is th e decim a l eq ui valen t o f t h e b i na r y co de lo aded in t h e 8-b i t rd a c r e g i s t er . r ab is th e end-to-end r e sis t an c e . r w is th e wi p e r r e sis t a n ce con t r i b u t e d b y the o n r e sis t an ce o f th e i n t e rn al sw i t c h . i n su mmar y , if r ab = 10 k? a n d t h e a t e r m ina l is o p en c i r c u i t e d , th e n th e f o ll o w i n g o u t p u t r e s i s t a n ce r wb is s e t fo r t h e indi ca te d r d a c la tch co des. ta ble 6. co des a nd corr es po n d i n g r wb resist an ce d (dec.) r wb (?) o u tput s t a t e 255 9,961 f u ll s c ale (r ab C 1 lsb + r w ) 1 2 8 5 , 0 6 0 m i d s c a l e 1 1 3 9 1 l s b 0 100 z e r o s c ale ( w iper c o n t ac t r e sistanc e ) n o t e th a t i n th e z e r o - s cal e c o n d i t i o n , a f i n i t e wi pe r r e s i s t a n ce o f 100 ? is p r es en t. ca r e sh o u ld b e tak e n t o limi t t h e c u r r en t f l o w b e tw e e n w an d b in t h is s t a t e to a maxim u m pu ls e c u r r en t o f n o m o r e tha n 2 0 m a . ot h e r w is e , deg r ada t io n o r p o s s i b le dest r u c t io n o f t h e in t e r n a l s w i t ch co n t ac t can o c c u r . simi lar to t h e me chanic a l p o te n t io meter , t h e r e s i st an ce o f t h e r d a c betw een th e w i per w a n d t e rm i n al a also p r od uces a dig i tal l y co n t r o l l ed co m p lem e n t a r y r e sis t a n ce, r wa . w h e n t h es e t e rm i n a l s a r e u s e d , th e b t e rm i n a l c a n b e o p e n ed . se t t i n g th e re s i st anc e v a lu e f o r r wa st ar ts a t a max i m u m va lue o f r e sist an ce a n d d e c r e a s e s a s t h e d a ta l o a d ed i n th e la t c h i n c r e a s e s i n v a l u e . the ge n e ra l e q u a t i o n fo r t h is o p era t io n is w ab wa r r d d r 2 256 256 ) ( ( 2 ) fo r r ab = 10 k? a n d t h e b t e r m in al o p en cir c ui ted , t h e f o ll o w i n g o u t p u t r e s i s t a n ce r wa is s e t fo r t h e i n dica t e d r d a c la t c h co des. ta ble 7. co des a nd corr es po n d i n g r wa resist an ce d (dec.) r wa (?) o u tput s t a t e 2 5 5 1 3 9 f u l l s c a l e 1 2 8 5 , 0 6 0 m i d s c a l e 1 9 , 9 6 1 1 l s b 0 1 0 , 0 6 0 z e r o s c a l e t y p i cal de vice-to-de vic e m a t c hin g is p r o c es s lo t dep e nden t an d ca n va r y b y u p to 30%. b e c a us e t h e r e sist an ce e l e m en t is p r o c es s e d in thin f i lm t e chn o log y , th e cha n g e in r ab wit h t e m p era t ur e has a v e r y lo w 45 p p m/ c t e m p er a t ur e co ef f i cien t.
ad5245 rev. b | page 14 of 20 programm ing t h e po tent iomet e r divi der voltage o u tp ut ope r ation t h e digi t a l po t e n t io m e ter easil y g e n e ra t e s a v o l t a g e di vid e r a t wip e r - to - b and wip e r - to - a prop or t i ona l to t h e i n put volt age a t a t o b . u n like t h e p o la r i ty o f v dd t o gn d , w h ic h m u s t be p o s i t i ve, volt age ac ro ss a to b , w to a, and w to b c a n b e a t ei t h er p o la r i ty . a v i w b v o 03 43 6- 0 3 6 fig u re 3 7 . pot e n t i o m et e r m o d e c o nf ig urat i o n i f ig n o r i n g t h e e f fe c t o f t h e wi p e r r e sist a n ce fo r a p p r o x ima t io n, t h e n c o n n e c t i ng t h e a te r m i n a l to 5 v and t h e b te r m i n a l to gr o u n d p r o d uces a n o u t p u t v o l t a g e a t t h e wi p e r - t o -b s t a r tin g a t 0 v u p t o 1 ls b les s tha n 5 v . e a c h ls b o f v o l t ag e is eq ual t o the v o l t a g e a p p l ied acr o s s t e r m inal a a n d b divide d b y t h e 256 p o s i t i ons of t h e p o te n t i o me te r d i v i d e r . t h e ge ne r a l e q u a t i on def i ning t h e o u tp u t vol t a g e a t v w wi t h r e s p e c t to g r o u n d fo r a n y va li d in p u t v o l t a g e a p pl ie d t o t e r m ina l s a and b is b a w v d v d d v 256 256 256 ) ( + = ( 3 ) a m o r e ac c u ra te calc u l a t io n, w h ic h in cl udes t h e ef f e c t o f wi p e r re s i st anc e , v w , is b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = ( 4 ) ope r a t i o n o f th e d i g i tal po t e n t io m e t e r i n th e di v i de r m o d e re su lt s i n a more a c c u r a t e op e r a t i o n o v e r te m p e r a t u r e. u n l i ke t h e rh e o st a t mo de , t h e o u t p u t vol t a g e is dep e n d en t mainly o n th e ra ti o o f th e in t e rn al r e s i s t o r s, r wa an d r wb , no t the a b s o l u t e val u es. th er efo r e , t h e t e m p er a t u r e dr if t r e d u ces t o 15 p p m / c. esd protection a l l d i g i t a l i n put s ar e pr ot e c te d w i t h a s e r i e s of i n put re s i s t or s a n d pa ral l e l z e n e r es d str u c t ur es, sh o w n in f i gur e 38 a n d f i gur e 39. this a p pl ies t o t h e dig i t a l in pu t p i n s sd a, sc l, a n d ad0. lo gic 34 0 ? gn d 0 34 36 - 0 3 7 fig u re 3 8 . e s d pr ot ect i o n of dig i t a l pi ns a, b , w gn d 0 343 6- 03 8 fig u re 3 9 . e s d pr ot ect i o n of r e s i s t o r t e r m in als terminal voltage operating ra nge the ad5245 v dd a n d gn d p o w e r su p p ly def i n e s t h e b o u n dar y c o ndi t i o ns for prop e r 3 - te r m i n a l di g i t a l p o te n t i o me te r o p era t ion. s u p p ly sig n als p r es en t o n t e r m inals a, b , an d w t h a t e x ceed v dd o r gnd a r e cla m p e d b y t h e i n t e r n al fo r w a r d-b i as e d d i od es (see f i g u r e 40). gn d a w b v dd 03 43 6 - 03 9 fig u re 4 0 . m a x i mu m t e r m in a l v o lt ag es set by v dd and g nd power-up sequence b e ca us e t h e esd p r o t e c t i o n di o d es limi t t h e vol t a g e co m p l i ance a t t e r m in als a, b , a n d w (see f i gur e 40), i t is im p o r t a n t t o po w e r v dd a n d gn d bef o r e a p p l yin g a n y v o l t a g e t o t e r m in als a, b , an d w ; o t h e r w ise , t h e d i o d e is f o r w a r d b i ased s u ch tha t v dd is p o w e r e d unin t e n t io na l l y a n d can a f fe c t t h e r e st o f t h e us er s cir c ui t. th e ideal p o w e r - u p s e q u en ce is in t h e f o l l o w in g ord e r : g n d , v dd , dig i t a l in p u ts, a n d t h en v a , v b , a n d v w . the rel a t i ve ord e r of p o we r i ng v a , v b , v w , an d t h e dig i t a l i n p u ts is not i m p o r t an t a s l o ng a s t h e y are p o we re d af te r v dd an d g n d . layout and power supply b y passing i t is g o o d p r ac tice t o em p l o y co m p ac t, m i nim u m lead len g t h la yo u t des i g n . th e leads t o t h e in p u ts sh o u ld be as dir e c t as p o s s i b le wi t h a m i nim u m co n d uc t o r len g th. g r o u nd p a th s s h o u ld h a v e l o w r e s i s t a n c e a n d lo w in d u cta n c e . s i m i la r l y , i t is al so g o o d p r ac tic e t o b y p a s s t h e p o w e r s u p p lies wi th q u al i t y ca p a ci t o rs f o r o p tim u m s t ab ili t y . s u p p l y leads t o th e de vice sh o u l d b e b y p a s s ed wi th disk o r c h i p cera m i c ca p a ci t o rs o f 0.01 f t o 0.1 f . lo w es r 1 f t o 10 f ta n t al u m o r e l ec tr o l ytic ca p a ci t o r s sh o u l d also b e a p p l ie d a t t h e s u p p l i es to min i mi ze an y t r ansien t di st u r b a nc e and l o w f r e q uenc y r i p p l e (see f i gur e 41). n o t e t h a t the digi tal gr o u n d s h o u ld also be jo in ed r e m o te l y t o th e an alog gr o u n d a t o n e p o in t t o min i m i ze th e gr o u n d bo un ce . v dd gn d v dd c3 10 f c1 0. 1 f a d 5245 + 03 43 6 - 04 0 figure 41. power s u pply bypassing
ad5245 rev. b | page 15 of 20 constant bias to retain resistance setting f o r us ers wh o desir e n o n v ol a t ili t y b u t ca nn ot j u s t if y t h e addi tio n al cost fo r th e eemem, th e ad5245 c a n b e co n s ider ed a lo w cos t a l t e r n a t i v e b y m a in t a inin g a co ns tan t b i as t o r e ta in th e wi p e r s e t t ing. th e ad5245 is desig n ed sp ec if ical l y wi t h lo w p o w e r in m i nd , which al lo ws lo w p o w e r co ns u m p t io n ev en in b a t t e r y -o p e ra t e d syst em s. f i gure 42 de m o n s t r a t es t h e p o w e r co n s um p t io n f r o m a 3.4 v , 450 m a -hr li-i on c e l l p h on e ba t t er y th a t i s co nn ec t e d t o t h e ad 5245. t h e m e a s u r em en t o v e r t i m e s h ow s t h at t h e d e v i c e d r a w s ap p r ox i m at e l y 1 . 3 a a n d co n s u m es n e g l ig i b le p o w e r . o v er a co urs e o f 30 da ys, the ba t t e r y is d e p l eted b y les s tha n 2% , t h e ma jo r i ty o f whic h is d u e t o t h e in t r in sic l e aka g e c u r r en t o f t h e b a t t e r y i t s e lf. da y s b a tt e r y l i f e d e p l et ed 0 90 % 92 % 94 % 96 % 51 0 1 5 98 % 100% 10 2% 10 4% 10 6 % 10 8 % 11 0 % 20 2 5 3 0 t a = 2 5 c 03 43 6- 0 4 1 figure 4 2 . b a ttery operat ing lif e d e p l eti o n t h i s d e m o n s tra t e s th a t co n s ta n t l y b i a s in g t h e p o t e n t i o m e t e r ca n be a p r ac tic a l a p p r o a c h . m o s t p o r t a b le de vices do n o t r e q u ir e t h e r e mo val o f b a t t er ies fo r cha r g i n g . al t h o u g h t h e r e sis t a n c e s e t t in g o f th e ad5245 is los t w h en t h e ba t t e r y n e ed s r e p l a c em en t , su ch e v en t s occu r ra t h e r i n f r eq u e n t l y s o t h a t t h is i n con v enie n c e is j u st if ie d b y t h e lo wer cost a n d sm al ler size o f fer e d b y t h e ad5 245. i f t o tal p o w e r is los t , then t h e us er sh o u ld b e p r o v i d e d wi t h a m e an s t o ad j u st t h e s e t t i n g acco r d ing l y . evaluation board a n eval ua ti o n b o a r d , alo n g wi t h all n e ces s a r y s o ftw a r e , i s a v a i la b l e t o p r og ra m the ad52 45 f r o m a n y pc r u nnin g w i ndo w s? 98/2 000/xp . th e g r a p hical us er in t e r f ace , as sh o w n in f i gur e 43, is st ra ig h t fo r w a r d a n d e a sy t o us e . m o r e det a i l e d info r m a t io n is a v a i lab l e i n t h e u s er ma n u a l , whi c h is p r o v ide d wit h t h e b o a r d . 03 43 6- 0 4 2 fig u re 4 3 . a d 52 4 5 e v aluat i on bo ard s o f t war e the ad5245 s t a r ts a t m i ds cale u p o n p o w e r - u p . t o in cr em en t or de cr em e n t t h e r e sist a n c e , t h e us er ca n si m p ly mo v e t h e s c r o l l - b a rs o n t h e lef t . t o wr i t e a sp e c i f ic val u e , t h e us er sh o u l d us e t h e b i t p a t t e r n i n t h e u p p e r s c r e e n and click t h e ru n bu tt o n . t h e f o r m a t o f wr i t in g da ta t o the de vice is sh o w n in t a b l e 8. t o r e ad t h e da t a f r o m t h e de vic e , t h e u s er ca n si m p ly click t h e re a d button . t h e f o r m a t of t h e re a d bit s i s s h ow n i n t a bl e 9 .
ad5245 rev. b | page 16 of 20 i 2 c interface i 2 c-compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 45). the next byte is the slave address byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5245 has one configurable address bit, ad0 (see table 8). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. on the other hand, if the r/ w bit is low, the master writes to the slave device. 2. in write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is a dont care. the second msb, rs, is the midscale reset. a logic high on this bit moves the wiper to the center tap, where r wa = r wb . this feature effectively overwrites the contents of the register; therefore, when taken out of reset mode, the rdac remains at midscale. the third msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. also during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the remainder of the bits in the instruction byte are dont cares (see table 8). 3. after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 45). 4. in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with write mode, in which eight data bits are followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46). 5. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 45). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 46). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output updates on each successive byte. if different instructions are needed, then the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5245 rev. b | page 17 of 20 table 8 . write mode s 0 1 0 1 1 0 a d 0 w a x r s s d x x x x x a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p sl a v e a ddr e s s byt e i n s t ruc t i o n byt e da ta byt e table 9. r e ad mode s 0 1 0 1 1 0 a d 0 r a d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a p sla v e a ddr ess b y te da ta b y te s = st ar t c o ndition p = st op c o ndition a = a c k n o wled g e x = don t car e w = w r ite r = r e ad rs = r e set wiper to mid scale 0x 80 sd = shutd o wn c o nnec t s wiper to b ter minal an d open cir c uits a t e rminal , but does not chang e c o n t en ts of wiper r e g i st er d7, d6, d5, d4, d3, d2, d1, d0 = da ta bits t 1 t 3 t 4 t 2 t 7 t 8 t 9 ps p s t 10 t 5 t 9 t 8 sc l sd a t 2 t 6 0 34 36 - 0 4 3 figure 44. i 2 c interf ace det a iled ti mi n g di ag ra m sc l f r am e 1 f ram e 2 st a r t by m a st er ack b y ad5245 s l a v e a d dre s s by t e st op b y ma s t e r i n s t ruct i o n b y t e sd a 0 1 0 1 1 0 ad0 r/ w xr s x x x x x 1 9 19 d7 d6 d5 d 4 d 3 d 2 d1 d 0 a ck b y a d 524 5 f ram e 3 da t a b y t e 1 9 ac k b y ad 5 245 sd 0 343 6- 04 4 fi gure 45 . wri t i n g t o the rdac r e gi ster no ac k b y m a st er sc l sd a 01 0 1 1 0 a d 0 r / w d7 d6 d5 d4 d 3 d2 d 1 d0 1 9 1 9 f ram e 1 fr a m e 2 s t art b y ma st e r ack b y ad5245 s l a v e addre s s by t e r dac re g i s t e r st op b y m a st er 0343 6- 045 fig u re 4 6 . r e adi n g dat a f r o m a prev io us ly sel ected r d a c r e gister in wr ite m o de
ad5245 rev. b | page 18 of 20 multiple devi ces on one b u s f i gur e 47 sh o w s tw o ad5245 devices o n t h e s a m e s e r i al b u s. e a ch has a dif f er en t sla v e addr ess b e ca us e t h e st a t es o f t h eir ad0 p i n s a r e di f f er en t. this al l o ws t h e r d a c wi t h i n e a ch d e vice t o b e wr i t t e n t o o r r e ad f r o m in d e p e n d en tl y . the m a s t er de vice s o u t p u t b u s li n e dr i v ers a r e o p en- d ra i n p u l l -do w n s in a full y i 2 c-co m p a t i b le in t e r f ace . ma st er a d 5245 sd a s c l r p r p +5 v +5 v sd a sc l sd a s c l a d 5245 ad0 ad0 034 36 - 0 4 6 fig u re 4 7 . m u lt ip le a d 52 45 dev i ces on one i 2 c bus
ad5245 rev. b | page 19 of 20 outline dimensions 13 5 6 2 8 4 7 2. 90 bs c 1. 60 bs c 1.95 bsc 0. 65 bs c 0. 38 0. 22 0. 15 m a x 1. 3 0 1. 1 5 0. 9 0 seating plane 1 . 45 m a x 0. 2 2 0. 0 8 0. 6 0 0. 4 5 0. 3 0 8 4 0 2. 80 bs c pin 1 indicator compliant to jedec standards mo-178-ba fig u re 4 8 . 8-le ad s m a l l out l ine tr ans i s t or p a ck ag e [sot- 23] (rj-8) dim e nsio ns sho w n i n mi ll im e t er s ordering guide m o d e l t e mper a t ur e r a n g e p a c k a g e d e s c r i p t i o n p a ck a g e o p t i o n br a n d i n g r ab (?) o r dering q u an tit y ad5245brj5-r2 C40c to +125c 8-l e ad so t - 23 rj-8 d0g 5 k 250 ad5245brj5-rl 7 C40c to +125c 8-l e ad so t - 23 rj-8 d0g 5 k 3,000 ad5245brjz5-r2 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0g 5 k 250 ad5245brjz5-rl7 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0g 5 k 3,000 ad5245brj10-r2 C40c to +125c 8-l e ad so t - 23 rj-8 d0h 10 k 250 ad5245brj10-rl7 C40c to +125c 8-l e ad so t - 23 rj-8 d0h 10 k 3,000 ad5245brjz10-r2 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0h 10 k 250 ad5245brjz10-rl7 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0h 10 k 3,000 ad5245brj50-r2 C40c to +125c 8-l e ad so t - 23 rj-8 d0j 50 k 250 ad5245brj50-rl7 C40c to +125c 8-l e ad so t - 23 rj-8 d0j 50 k 3,000 ad5245brjz50-r2 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0j 50 k 250 ad5245brjz50-rl7 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0j 50 k 3,000 ad5245brj100-r2 C40c to +125c 8-l e ad so t - 23 rj-8 d0k 100 k 250 ad5245brj100-rl7 C40c to +125c 8-l e ad so t - 23 rj-8 d0k 100 k 3,000 ad5245brjz100-r2 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0k 100 k 250 ad5245brjz100-rl7 1 C40c to +125c 8-l e ad so t - 23 rj-8 d0k 100 k 3,000 ad5245e v a l 2 e v alua t i o n boar d 1 z = pb-free part. 2 th e eval uat i on board is s h ippe d with the 10 k ? r ab re si st or opt i on ; h o w e ver, t h e boa r d i s com p a t i b le wi t h a ll a v a i l a b le r e si st or va lu e opt i on s.
ad5245 rev. b | page 20 of 20 notes pur c has e o f licen s ed i 2 c c o m p one n t s of a n a l o g d e v i c e s or on e of it s su bl i c e n s e d ass o c i a t e d c o m p an i e s c o n v e y s a l i c e n s e f o r t h e p u r c h a ser un d e r th e ph ili p s i 2 c p a t e n t r i g h ts to us e t h es e co m p o n e n ts in an i 2 c syst em, p r o v i d e d t h a t t h e syst em co nfo r m s to t h e i 2 c s t a n da rd s p e c if ica t io n as def i ne d b y p h i l i p s. ?2006 analo g devi ces, inc. all rights reserve d . tra d em ar ks and registered tra d emar ks are the prop erty of their respective o w ners . c 03436-0-1/06(b)

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